The simplest method of transferring data through the inputs or outputs of a silicon chip is to directly connect each bit of the datapath from one chip to the next. pdf. High speed serial link design (SERDES) Introduction, Architectures and applications ARCHITECTURE OF HIGH-SPEED SERDES main device in this operation. If a protocol application requires “full duplex” communication, then. When most system designers look at serializer/deserializer (SerDes) devices, they often compare Networking Group, handling high-speed interface products.
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High Speed Serdes Devices and Applications provides a broad The material focuses on HSS devices, and the consolidation of related topics into a s. PDF · HSS Architecture and Design. James Donald Rockrohr. Pages PDF. Rockrohr. High Speed Serdes Devices and Applications. ▷ Provides information on the features and functions typically found on HSS devices. ▷ Explains how. Download High Speed Serdes Devices and Applications By Davi pdf · Read Online High Speed Serdes Devices and Applications By Da pdf.
It may use an internal or external phase-locked loop PLL to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also make use of a double-buffered register to avoid metastability when transferring data between clock domains. The receive clock may have been recovered from the data by the serial clock recovery technique. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer.
However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream.
The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side. The serialized stream is sent along with a reference clock. The clock jitter tolerance at the serializer is ps rms. Embedded clock SerDes[ edit ] An embedded clock SerDes serializes data and clock into a single stream.
Once the parallel data is latched in, the to-1 multiplexer in the Serializer converts the bit parallel data into a serial data stream. The conversion is done with the clocks generated from the transmit clock generator. A high-speed clock running at the serial data rate is usually required.
To reduce cost, this high-speed clock is normally generated from an off-chip low-frequency quartz crystal. A design challenge for the PLL is to maintain a minimum amount of clock jitter despite all the switching noise generated by the digital logic in the ASIC.
For PCI Express, the clock jitter has to be low enough so that the total serial output jitter is less than ps.
In addition, for the proper operation of the to-1 multiplexer, the PLL generated high-speed clock has to maintain a fixed timing relationship with the MHz clock used for latching in the parallel data. With a bit time of ps, it is not a trivial task to keep a constant phase relationship between the two clocks over all the temperature, supply voltage and process corners.
When multiple bits of the same polarity are output in succession, all the subsequent bits are driven with amplitude 3. Figure 6 shows a waveform with de-emphasis. In addition, the output impedance of the line driver has to be able to switch from low impedance to high impedance and vice versa during these low power states. Furthermore, to detect whether a receiver is present at the far end of the link, PCI Express requires the line driver to have the capability of changing its output common-mode voltage and monitoring the rate that the outputs change to the new value.
Figure 6. Transmitted waveform with de-emphasis On the receiver side, there is an input monitoring circuit that monitors the activities on the serial data inputs. When the input differential voltage goes above mV, the input monitoring circuit needs to signal the presence of valid data on the inputs.
As a result, the De-serializer has to be able to handle an input data stream with a peak-to-peak amplitude as low as mV differential. The received serial data is retimed with the clock recovered from the incoming data stream.
Therefore, the clock recovery circuit in the De-serializer has to filter out all these timing jitter i. In addition to timing jitter, the input signals could have a frequency offset up to ppm from the local clock.
The clock recovery circuit has to have a bandwidth wide enough to track this frequency offset. For systems that implement the Spread Spectrum Clock option specified in PCI Express, the clock recovery circuit also has to track the frequency fluctuation caused by the Spread Spectrum Clock.
Once the serial data is retimed with the recovered clock, it can be converted back to a bit wide data stream with the 1-to de-multiplexer. Similar to the to-1 multiplexer in the Serializer, the operation of the1-to de-multiplexer usually requires a high-speed bit clock that is synchronized with a lower speed byte clock. Since the bit time for PCI Express is only ps, the two clocks would have to track each other within as low as ps depending on the setup and hold time needed by the latch.
When the Byte Alignment Circuit is enabled, it looks for the comma characters and aligns the bit outputs with the comma characters. The aligned parallel data is sent to the ASIC along with the recovered byte clock. What makes a SerDes stand out from others? Some of the challenges in designing a multi-gigabit SerDes have been outlined in the previous section. A good SerDes design has to solve these design problems while keeping power consumption low and footprint small.
In this section, we will discuss some of the circuit design techniques that can be employed to tackle these design challenges. We will also discuss some of the features that can make a SerDes design stand out. Better jitter performance For a multi-gigabit SerDes, its jitter performance is one of the most important parameters for judging the robustness of the design since the bit error rate is directly affected by the jitter performance.
To achieve a BER of 1x, PCI Express specifies a maximum output jitter of ps for the Serializer and a minimum input jitter tolerance of ps for the De-serializer.
For the Serializer, a smaller output jitter means it is less likely that a bit error will occur when the data is received by the De-serializer. The serial clock is typically generated by a PLL-based frequency multiplier from a slower reference clock.
Simplified block diagram of a clock-multiplying PLL In addition to the PLL, there are other areas where improvements can be made to reduce the serial output jitter. For example, the clocking on the to-1 multiplexer; paying attention to the layout on power and ground; employing an auto-calibration circuit to do the on-chip termination; dealing electrical properties carefully on packaging.
Since the received data is retimed by latching the data with the recovered clock, a bit error can occur only if either the clock or the data is too early or too late.
The recovered clock is generated by the clock recovery circuit in the De-serializer. The clock recovery circuit is usually based on a PLL similar to the one shown in Figure 7. But, contrary to a frequency-multiplying PLL, the input to the clock recovery circuit is the incoming serial data instead of a stable reference clock. For PCI Express, the frequency of the clock embedded in the incoming data can deviate from the local clock by ppm.
As a result, the PLL in the clock recovery circuit must have a loop bandwidth wide enough to track this frequency difference.
The amount of jitter on the received data can potentially be reduced by an on-chip equalizer. The purpose of the equalizer is to reverse the high-frequency attenuation caused by the PCB traces or cables. For PCI Express, the de-emphasis circuitry in the Serializer has already pre-equalized the data before it is transmitted. Therefore, the need for an equalizer in the De-serializer is diminished.
Common parallel bus Embedded clock bits SerDes are well suited to non-byte- widths for these chipsets include , , and bits. Embedded Clock SerDes: The bit transmission codes were developed by Fig. Two multiple edge transitions every cycle as well as DC balance clock bits, one low and one high, are embedded into the serial balanced number of transmitted ones and zeros. DC balance facilitates driving creating a periodic rising edge in the serial stream.
Data AC-coupled loads, long cables and optical modules. After powering up, the receiver automatically searches for the periodic embedded clock rising edge.
Once locked, the receiver recovers boundaries in the serial stream, the transmitter first marks one data from the serial stream regardless of payload data pattern. This is an especially useful feature in systems marker for receiver code alignment. Once code alignment is where the receiver is in a remote module not under direct accomplished, the receiver maps the bit codes back to byte system control.
Since the receiver is locked to the incoming data, flagging an error if it detects an invalid 10b code. As a result, they typically require tight Embedded clock bits SerDes are especially well suited to external clock source frequency and jitter control.
For Ottawa, Canada. While this scheme does not count total bit errors, it is a good way to monitor serial link performance. Bit Interleaving SerDes: The receiver demultiplexes the bits back into the original slower streams. Note that a serial stream coming into transmitter input channel 1 may not come out on receiver output channel 1. This is not regarded as a problem in the applications because the serial streams contain independent cell or packet data that is processed downstream.