PCI uses a shared parallel bus. – Bandwidth shared between devices on the bus. – Only one device may own the bus at any time. Pci Express System Architecture - Free ebook download as PDF File .pdf), Text File .txt) or read book online for free. PCI and PCI Express Bus Architecture. Computer Science Peripherals can be moved between computer systems that use the same bus .. echecs16.info).
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PCI Express. System. Architecture. MINDSHARE, INC. Ravi Budruk. Don Anderson. Tom Shanley. Technical Edit by Joe Winkles. ADDISON-WESLEY. PCI Express System Architecture Introduction to PCI Express: A Hardware and Software Developer's Guide solution manual computer system architecture. M. Morris Mano.1l Computer architecture is concerned with the structure and behav. is explained The Architecture of Computer Hardware and System.
It provides power, cooling, and a communication bus to support multiple instrumentation modules within the same enclosure. PXI Express maintains PXI features to ensure backward compatibility while providing more bandwidth, power, cooling, and timing and synchronization features in addition to the standard PXI features. Back to top Hardware Overview The PXISA hardware specification stipulates all feature requirements pertaining to the mechanical, electrical, and software architectures. Subsequent sections in this paper break down these hierarchies to go into each section in additional detail and explain how they specifically apply to PXI. Figure 2. For example, through the mechanical architecture, the system controller is defined to be in the leftmost slot of a PXI chassis to ensure it is at the left end of the PCI bus segment. It simplifies the integration and increases the degree of compatibility between chassis and controller options with this defined location.
The memory controller today is integrated into the CPU. Post memory initialization. Therefore, the platform firmware binary usually copies itself to RAM in this step and continues execution there.
In the previous step, the main memory RAM is initialized.
However, there are several more steps required before the main memory RAM can be used to execute the platform firmware code: Memory test. The detail of how the test is carried out depends on the boot time requirement of the system. You can read details of the mapping in the respective chipset datasheet. Redirecting memory transaction to the correct target. The details depends on the platform CPU and chipset combination , and the runtime setup, i.
Setting up the stack. This step sets up the stack in RAM to be used for further platform firmware code execution. In previous steps, the stack is assumed to be present in the CAR. Transferring platform firmware execution to RAM. Miscellaneous platform enabling.
This step depends on the specific system configuration, i. Interrupt enabling.
Previous steps assume that the interrupt is not yet enabled because all of the interrupt hardware is not yet configured. In this step the interrupt hardware such as the interrupt controller s and the associated interrupt handler software are initialized. After the hardware and software required to handle the interrupt are ready, the interrupt is enabled. Timer initialization. In this step, the hardware timer is enabled.
The timer generates timer interrupt when certain interval is reached. OS and some applications running on top of the OS use the timer to work. Memory caching control initialization. The caching of the memory ranges depends on the type of hardware present in the respective memory range and it must be initialized accordingly. Application processor s initialization.
The non-bootstrap CPU processor core is called the application processor AP in some documentation; we will use the same naming here. Therefore, the other cores—the AP—must be initialized accordingly before the OS boot-loader takes control of the system.
This initialization depends on the system configuration. The embedded controller is mostly found on laptops, it controls things such as buttons on the laptop, the interface from the laptop motherboard to the battery, etc. PCI device discovery and initialization. OS boot-loader execution. Now, the boot process carried out by the platform firmware should be clear to you.
Particularly the steps where the system address map is initialized in relation to PCI devices, namely step 3c and step The Intel E chipset is the implementation sample here. Figure 1 shows how the CPU connects logically to the rest of the system via the Intel E northbridge. This implies that any access to any device outside the CPU must pass through the northbridge.
In fact, that is how the northbridge works in practice. The difference with present-day systems is the physical location of the northbridge, which is integrated into the CPU, instead of being an individual component on the motherboard like Intel E back then. The platform firmware initializes these address mapping-related registers at boot to prepare for runtime usage inside an OS.
Now that you know how the system address map works at the physical level, i. Figure 2 shows the system address map of systems using Intel E chipset. You can find a complementary address mapping explanation in Intel E chipset datasheet in Section 4. Despite that, the amount of memory space used depends on the memory controller in the system, which in this case located in the northbridge Intel E chipset. Therefore, this implies that the memory range consumed by the PCI devices is relocatable, i.
In the—very old—ISA bus, you have to set the jumpers on the ISA device to the correct setting; otherwise there will be address usage conflict in your system. Some of the special ranges above TOM are hardcoded and cannot be changed because the CPU reset vector and certain non-CPU chip registers always map to those special memory ranges, i. These hardcoded memory ranges cannot be used by PCI devices at all.
Otherwise, the device will not be regarded as a valid PCI device. The PCI configuration register consists of bytes of registers, from byte offset 00h to byte offset FFh. The byte PCI configuration register consists of two parts, the first 64 bytes are called PCI configuration register header and the rest are called device-specific PCI configuration register. There are two types of PCI configuration register header, a type 0 and a type 1 header.
Figure 3 shows the PCI configuration register type 0 header.
BARs span the range of six bit registers bytes , from offset 10h to offset 27h in the PCI configuration header type 0. It works like this: Different systems can have different main memory RAM size. Because both of them are modifiable, you can change the memory range occupied by the PCI device memory in the CPU memory space as required. We call this configuration the first system configuration from now on.
The same system as in point 1. However, we add new mb RAM module. We call this configuration the second system configuration from now on.
Figure 4 shows the system address map for the first system configuration mb RAM and the system address map for the second system configuration mb RAM. The change also causes the base address of the AGP video card memory to change; in the first system configuration the base address is mb while in the second system configuration the base address is mb.
In the first system configuration, the platform firmware initializes the video memory to be mapped in memory range mb to mb, because the video memory size is 32 mb—the first mb is mapped to RAM. The northbridge logic checks all of its registers related to address mapping to find the device that match the address requested. Note that initialization of the four address mapping registers is the job of the platform firmware.
The northbridge forwards the result returned by the video card to the CPU. After this step, the CPU receives the result from the northbridge and the read transaction completes. If you look at the system address map in Figure 2, you can see that there are two more memory ranges in the system address map that show up mysteriously. Both of these memory ranges are not accessible in normal operating mode, i. This memory range is relocatable, depending on the size of main memory.
At this point, everything regarding system address map in a typical Intel E-ICH2 system should be clear. The one thing remaining to be studied is initialization of the BAR. There are some additional materials in the remaining sections, though. They are all related to system address map. The formats of these two types of BARs are quite different.
Figure 6 and Figure 7 show the formats of both types of BAR. Actually, only the lowest bit matters; it differentiates the type of the BAR, because the bit has a different hardcoded value when the BAR types differ. You can see this difference in Figure 6 and Figure 7.
This article deals with this type of BAR because the focus is on the system address map, particularly the system memory map. Since the introduction of the original PCI bus back in the early 90's, very little has changed in the way that data is handled inside the computer. The PCI bus has served well for the last 10 years and it will play a major role in the next few years. Streaming data from various video and audio sources are now commonplace on the desktop and mobile machines and there is no baseline support for this time-dependant data within the PCI 2.
Applications such as video-on-demand and audio re-distribution are putting real-time constraints on servers too. Many communications applications and embedded-PC control systems also process data in real-time. Today's platforms, Figure 1. As successful as the PCI architecture has become, there is a limit to what can be accomplished with a multi-drop, parallel shared bus interconnect technology.
PCI Express is the natural successor to PCI, and was developed to provide the advantages of a state-of-the-art, high-speed serial interconnect technology and packet based layered architecture, but maintain backward compatibility with the large PCI software infrastructure. The key goal was to provide an optimized and universal interconnect solution for a great variety of future platforms, including desktop, server, workstation, storage, communications and embedded systems.
It will maintain complete hardware and software compatibility with all recent PCI devices. It is expected that PCI will coexist in many platforms to support today's lower bandwidth applications until a compelling need, such as a new form factor, causes a full migration to a fully PCI Express based platform.