PDF | On Jan 1, , Dr. Moorthi Madhavan and others published EC MICROPROCESSOR AND MICROCONTROLLER. Engineering Class handwritten notes, exam notes, previous year questions, PDF free download. Difference Between Microprocessor and. Microcontroller: Microprocessor: The microprocessor is a small computer or CPU (central processing unit) used to do.
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Lecture Note. On. Microprocessor and Microcontroller. Theory and Applications. Subject Code:BEE Semester: 5 th. Branch: EE and EEE. Download Microprocessor and Microcontroller System By A. P. Godse, D. A. Godse – Introduction CPU, Address bus, Data bus and control bus. Input/Output. The Microcontroller and Embedded Systems Using Assembly and C Second Edition Muhammad Ali Understanding / Microprocessors and.
The term microprocessor and microcontrolle r have always been confused with each other. Both of them have been designed for real time application. They share many common features and at the same time they have significant differences. They are available in different version starting from 6 pin to as high as 80 to pins or even higher depending on the features. Nordic's nRF SiP solves complex wireless design challenges and possesses a comprehensive set of qualifications that are needed to utilize cellular technology through high integration and pre-certification for global operation. A depth-saving 2-stage filter further enhances EMC performance. Harwin's M connector series is a 2.
TLx is incremented from 0 to When TLx is incremented from , it resets to 0 and causes THx to be incremented by 1. Since this is a full bit timer, the timer may contain up to distinct values. If you set a bit timer to 0, it will overflow back to 0 after 65, machine cycles.
What is that, you may ask? When a timer is in mode 2, THx holds the "reload value" and TLx is the timer itself.
Thus, TLx starts counting up. When TLx reaches and is subsequently incremented, instead of resetting to 0 as in the case of modes 0 and 1 , it will be reset to the value stored in THx. Split Timer Mode mode 3 Timer mode "3" is a split-timer mode.
When Timer 0 is placed in mode 3, it essentially becomes two separate 8-bit timers. Both timers count from 0 to and overflow back to 0.
All the bits that are related to Timer 1 will now be tied to TH0. While Timer 0 is in split mode, the real Timer 1 i. TH1 and TL1 can be put into modes 0, 1 or 2 normally--however, you may not start or stop the real timer 1 since the bits that do that are now linked to TH0.
The real timer 1, in this case, will be incremented every machine cycle no matter what. If the result of the latest arithmetic operation is having MSB most. They are presented below in the order of theirpriority from lowest to highest: The processor has 5 interrupts. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3CH hexadecimal address. When this interrupt is received the processorsaves the contents of the PC register into stack and branches to 24H hexadecimal address.
When the interrupt occurs. SOD serial output data: RST 5. SID serial input data: This is used for transferring of data into the memory serially. The processor calls the subroutine. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34H hexadecimal address.
When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2CH hexadecimal address. This unit synchronizes all the microprocessor operation and generates control and status signal necessary for communication between the microprocessor and peripherals. Timing and Control Unit: ALE can also be used to strobe the status information.
WR Output 3state: Encoded status of the bus cycle: RD Output 3state: S1 Output: Data Bus Status.
A15 Output 3 State: Address Bus: ALE is never 3stated. ALE Output: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals.
The input frequency is divided by 2 to give the internal operating frequency. It is disabled by Reset and immediately after an interrupt is accepted.
INTR Input: The period of CLK is twice the X1. The processor can regain the buses only after the Hold is removed. Indicates CPlJ is being reset. INTA Output: It is recognized at the same time as INTR. When the Hold is acknowledged. HOLD Input: The signal is synchronized to the processor clock. It has the highest priority of any interrupt. The INTR is enabled and disabled by software. CLK Output: It is sampled only during thenext to the last clock cycle of the instruction.
It is unaffected by any mask or Interrupt Enable. X2 input period. If it is active. HLDA Output: X2 Input: Decoder It is used to select the memory chip of processor during the execution of a program. SID Input: Three types of memory is. SOD output: No of IC's used for decoder is. Ground Reference. The execution time is represented in T-states. It represents the execution time taken by each instruction in a graphical format.
They are 1. Machine cycles of The microprocessor has 5 seven basic machine cycles. Opcode fetch cycle 4T. Memory write cycle 3 T 4. Memory read cycle 3 T 3. Opcode fetch machine cycle of The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle. Memory Read Machine Cycle.
Memory Read Machine Cycle of Memory Write Machine Cycle 4. C7H from accumulator is now stored in A. It is fetched from the memory 41FFH see fig. MW machine cycle. The vector address for these interrupts can be calculated as follows. These instructions are inserted at desired locations in a program. Types of Interrupts: It supports two types of interrupts.
It is unaffected by any mask or interrupt enable. Hardware interrupts: This means hat the TRAP must go high and remain high until it is acknowledged. Input goes to high and stay high until it recognized.
It is disabled by. DI instruction 2. SIM instruction 2. After reorganization of interrupt. By resetting microprocessor External signal 2. System or processor reset.
Input goes to high and no need to maintain high state until it recognized. In response to the acknowledge signal. If INTR signal is high. After receiving INTA active low signal. The following sequence of events occurs when INTR signal goes high. On receiving the instruction. The checks the status of INTR signal during execution of each instruction.
In the case of multibyte instruction. Input goes to high and it is necessary to maintain high state until it recognized. RST 6. In the second instruction. Two-word or 2-byte instructions 3.
Each instruction has two parts: In some instructions. The operand or data can be specified in various ways. MOV rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is. These instructions are stored in 8- bit binary format in memory. In the first instruction. It may include 8-bit or bit data.
One-word or 1-byte instructions 2. Operand s are internal register and are coded into the instruction These instructions are 1-byte instructions performing three different tasks. Instruction word size The instruction set is classified into the following three groups according to word size: Three-word or 3-byte instructions In the For example The instruction would require two memory locations to store in memory.
MVI r. Note that the second byte is the low-order address and the third byte is the high-order address. Source operand is a data byte immediately following the opcode. MVI A. Since the byte is not the data but points directly to where it is located this is called direct addressing.
MOV A. Three-Byte Instructions In a three-byte instruction. This is an example of immediate addressing. The two data bytes are bit data in L H order of significance. This is also immediate addressing. In these instructions the source can be a register. HL used as bit registers. Indirect addressing. Direct addressing. Register addressing. This instruction would require three memory locations to store in memory. Immediate addressing. This is also an example of direct addressing.
For The sources and destination are operands. A or MVI A. Three byte instructions. The entire group of instructions. These instructions can be classified into the following five functional categories: Load the immediate data to the destination provided. Data Transfer Croup The data transfer instructions move data between registers or between memory and registers. Rs 3 Direct addressing Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device.
The second address is where the data is stored. Data is present in the instruction. Note that this requires several memory accesses. MOV Rd. MVI R. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H. And the contents of the address and the one following is used to form a second address.
The unconditional branching instructions are as follows: The logical AND. The conditions that may be specified are as follows: A LXI H.
C MOV H. M MOV M. A MVI H. Memory Organization. Two-Byte Instructions In a two-byte instruction. These instructions are 1-byte instructions performing three different tasks. Three-word or 3-byte instructions One-Byte Instructions A 1-byte instruction includes the opcode and operand in the same byte. Three-Byte Instructions. Operand s are internal register and are coded into the instruction. It is most often used to access RAM locations In a three-byte instruction.
R7 cannot be used to hold the address of an operand located in RAM when using indirect addressing mode. IE also exists a global disable bit. The "C" means code. MOVC A. It clears an external interrupt flag IE0 or IE1 only if it was transitionavtivated. Programmer must also be more careful with proper selection. The interrupt locations are spaced at 8-byte interval. TLx will count from 0 to Table 4. This also means. Timer SFR has two timers which each function essentially the same way.
We will discuss this use of timers first and will subsequently discuss the use of timers to count events.
This is a relic that was kept around in the to maintain compatability with its predecesor. The timers have three general functions: Generally the bit timer mode is not used in new development. When a timer is used to measure time it is also called an "interval timer" since it is measuring the time of the interval between two events. When the timer is in bit mode.
When TLx is incremented from If you set a bit timer to 0. It functions just like bit mode except that all 16 bits are used. JNB P1.
THx holds the "reload value" and TLx is the timer itself. Let's say we hooked the sensor to P1. While Timer 0 is in split mode. When TLx reaches and is subsequently incremented. How can this be useful?
Let's say you had a sensor placed across a road that would send a pulse every time a car passed over it. TLx starts counting up. When a timer is in mode 2. This is not terribly difficult. What is that. If a car hasn't raised the signal.
When Timer 0 is placed in mode 3. TH1 and TL1 can be put into modes 0. All the bits that are related to Timer 1 will now be tied to TH0.
This is a very commonly used mode. Microcontrollers are designed to perform specific tasks. Specific means applications where the relationship of input and output is defined.
Depending on the input, some processing needs to be done and output is delivered. For example, keyboards, mouse, washing machine, digicam, pendrive, remote, microwave, cars, bikes, telephone, mobiles, watches, etc. This in turn reduces the size and the cost. Microprocessor find applications where tasks are unspecific like developing software, games, websites, photo editing, creating documents etc.
In such cases the relationship between input and output is not defined.